In a multi-processor system having multiple processors and multiple caches, each cache may store a copy of a piece of data stored in memory. Problems arise when more than one cache contains a copy of the same piece of data. Various techniques have been developed to ensure data coherency across multiple caches. For example, when the data in one cache is modified, other copies of the data are marked as invalid so that they will not be used.
To help maintain cache coherency, many systems include a directory to aid in determining presence and state of data in cache lines of such multiple caches. The state of a cache line may indicate whether the line has only one valid copy outside of the main memory, has multiple valid copies shared by multiple caches, or has no copies outside of main memory (i.e., it has been invalidated in all caches).
Efficiency of cache coherency can improve overall performance of general-purpose processors. This is especially true for many-core processors and large-scale cache coherent non-uniform memory architecture (cc-NUMA) systems. Different systems can have many different cache coherence message types, each of which can have different timing criticality properties, due to hop imbalance root caused by directory indirection. However, existing systems do not differently handle these different message types.